As the microprocessors progress in performance and scale, personal computer systems (which use the microprocessors) move drastically to the multimedia environment for processing various information--such as text, sounds, graphics, animation, movie, and so forth. Such computer systems are now called multimedia computers. In order to achieve multimedia function, hardware devices such as a high performance video card, sound card, TV/radio card, modem, etc. are installed in the expansion slots of the computer main board. Also, peripheral devices such as CD-ROM drives and various kind of software drivers can be implemented. Further, the multimedia data fed from the above expansion boards or peripheral devices are transferred to the central processing unit (CPU) via local bus under control of the computer operating system. In order to enhance data transfer rate between the CPU and the peripheral devices, the Peripheral Component Interconnect (PCI) standard has been established. The basic features of the PCI bus are: it usually has 64 bits data structure and provides two operating voltages systems. Also, auto detection and auto setup (Plug and Play function) of the connected devices is available.
FIG. 1 shows the pin configurations of the conventional PCI bus connector or PCI slot. The connector 100 has a plurality of connector pins arranged in two rows. Each row, designated by A and B, has 94 pins. Pin numbers 1 to 62 of each row are used for the 32-bit data structure, and 63 to 94 are for the 64-bit data structure. Pins located at the first column of the rows is denoted by A1 and B1, and at the last column is denoted by A94 and B94. Each of the pins are connected by predetermined signal lines according to the PCI standard, and the arrangement thereof (for example, when used with 5 volts operating voltage) is shown in table I.
TABLE I ______________________________________ No B A ______________________________________ 1 -12V TRST# 2 TCK +12V 3 GND TMS 4 TDO TD1 5 +5V +5V 6 +5V INTA# 7 INTB# INTC# 8 INTD# +5V 9 PRSNT1 RESERVED 10 RESERVED 5V 11 PRSNT2 RESERVED 12 GND GND 13 GND GND 14 RESERVED RESERVED 15 GND RST# 16 CLK +5V 17 GND GNT# 18 REQ# GND 19 5V RESERVED 20 AD31 AD30 21 AD29 +3.3V 22 GND AD28 23 AD27 AD26 24 AD25 GND 25 +3.3V AD24 26 C/BE3# IDSEL 27 AD23 +3.3V 28 GND AD22 29 AD21 AD20 30 AD19 GND 31 +3.3V AD18 32 AD17 AD16 33 C/BE2# +3.3V 34 GND FRAME# 35 IRDY GND 36 +3.3V TRDY# 37 DEVSEL GND 38 GND STOP# 39 LOCK# +3.3V 40 PERR# SDONE 41 +3.3V SBO# 42 SERR# GND 43 +3.3V PAR 44 C/BE1# AD15 45 AD14 +3.3V 46 GND AD13 47 AD12 AD11 48 AD10 GND 49 GND AD09 50 BORDER 51 52 AD08 C/BE0# 53 AD07 +3.3V 54 +3.3V AD06 55 AD05 AD04 56 AD03 GND 57 GND AD02 58 AD01 AD00 59 +5V +5V 60 ACK64# REQ64# 61 +5V +5V 62 63 RESERVED GND 64 GND C/BE7# 65 C/BE6# C/BE5# 66 C/BE4# +5V 67 GND PAR64 68 AD63 AD62 69 AD61 GND 70 +5V AD60 71 AD59 AD58 72 AD57 GND 73 GND AD56 74 AD55 AD54 75 AD53 +5V 76 GND AD52 77 AD51 AD50 78 AD49 GND 79 +5V AD48 80 AD47 AD46 81 AD45 RESERVED 82 GND AD44 83 AD43 AD42 84 AD41 +5V 85 GND AD40 86 AD39 AD38 87 AD37 GND 88 +5V 3.3V 89 AD35 AD35 90 AD33 AD33 91 GND GND 92 RESERVED RESERVED 93 RESERVED GND 94 GND RESERVED ______________________________________
In table I, thc signals on the 32-bits data PCI bus are as follows:
CLK (clock). A signal line that supplies clock signals for operating PCI devices. PA1 RST#. A signal line for resetting a control device connected with the PCI bus. PA1 AD31.about.AD00. Address and data signal lines using multiplexed signaling schemes. Selection is made by using the signal lines FRAME#. Logical high of the FRAME# signal is indicative of usage for the data, and logical low for the address. PA1 C/BE0#.about.C/BE3#. Command or effective byte signal lines, operated in multiplex mode. Commands for the operation of the address, and effective byte for the data. PA1 PAR (Parity). Even parity for AD31.about.AD00 and C/BE0#.about.C/BE3# signal lines. PA1 FRAME#. Signal occurs during access to other device through PCI bus. For the time duration in the data processing, the signal is logical low. PA1 IRDY (Initiator Ready). A signal indicative of status of initiator device related to data transaction. PA1 TRDY# (Target Ready). A signal indicative of status of target device. PA1 STOP#. A request to stop transmittal of a signal from target device to initiator device. PA1 LOCK#. A signal occurring when multiple transactions are required for completion of the action in progress. PA1 IDSEL. (Initialization Device Select). A signal used for reading the configuration register provided in each of the peripheral devices, and used as a chip select signal when writing data in the configuration register. PA1 DEVSEL# (Device Select). As a result of decoding address lines, when a device is selected as a target device, the signal becomes active low. Otherwise, the active low signal is used to select a device on the PCI bus. PA1 REQ# (Request). A signal line requesting a grant of usage of the PCI bus to the arbitrator when a master device is about to use the PCI bus. PA1 GNT# (Grant). A signal indicating grant for the request for usage of the PCI bus. PA1 PERR# (Parity Error). A signal indicating that a problem is found in the data parity. PA1 SERR# (System Error). A signal indicating that a parity error, data parity, or other critical problems are found. PA1 INTA#, INTB#, INTC#, INTD#. Interrupt signal lines. PA1 SBO#, SDONE# (Snoop Backoff, Snoop Done). Signal lines for supporting cache function of the device having cacheable memory. PA1 TCK, TDI, TDO, TMS, TRST#. Signal lines provided for testing PCI devices. PA1 PRSNT1#, PRSNT2# (Present). Signal lines for reporting the installation of a PCI device in a slot, and information for the power dissipation thereof. PA1 AD63.about.AD32. Address/data signal lines with respect to the most 32 bits in total 64 bits. PA1 C/BE4.about.C/BE7. Signal lines indicative of command or effective byte for the most 32 bits data. PA1 REQ64#. Signal follows logical low when the 64-bit data structure is required. PA1 ACK64#. Responsive to the REQ64# signal, a signal indicative of the recognition of the target device. PA1 PAR64. Signals for reporting the status of parity regarding the most 32 bits in the 64-bit data. Even parity is applied.
Further, signal lines provided for the 64-bits data PCI bus are described as follows:
As is apparent from FIG. 1 and Table I, the conventional PCI bus is configured to transfer digital data or addresses through the address/data signal lines AD00.about.AD63. In addition, control signal lines are provided to control peripheral devices on the bus. Nevertheless, there are currently various audio/video apparatuses, for example digital satellite receivers, video disk players, CATV receiver sets, etc., other than the functional expansion board installed in the computer system. Therefore, a need arises for transferring the graphics and sound generated at an external audio/video source and handling them in the multimedia computer. To meet this need, an external cable is required to transfer audio or video signals from the output terminals of the audio/video source to the input terminals of the computer. When the number of the required external audio/video sources increases, increasing the number of connection cables and terminals is necessary. Therefore, the cable connection becomes complicated, and signal attenuation as well as noise occurs when analog formatted audio/video signals are transferred through the cable. Also, controlling the external audio/video apparatus by the computer using the external cable is difficult. Further, in conventional multimedia computers having Industry Standard Architecture and PCI bus connectors, there is a limitation of the number of available peripheral devices connected therewith. Thus, an improvement and further insight on the current art of peripheral connectors and multimedia is necessary.
On this matter, an exemplar of the contemporary practice and art, Buchala et al. (U.S. Pat. No. 5,638,521, Apparatus Using A Parallel Interface For Data Transfer Between A Plurality Of Computers, As Well As For Transfer Of Data From Computers To Shared Peripheral Devices, Jun. 10, 1997) discusses an apparatus having a plurality of computers for selective data transfer from the computers to, at least, one shared output device. Gajewski et al. (U.S. Pat. No. 5,630,175, Surround Sound System boor General Purpose Computer Using Dual Sound Cards, May 13, 1997) discusses surround sound channels being played or recorded using an audio card added to the computer system, which audio card controls additional speakers and/or microphones. Hosokawa (U.S. Pat. No. 5,630,167, Electronic Apparatus Having A Plurality Of Connectors Each Connecting to One Of A Plurality Of Kinds Of Cards, May 13, 1997) discusses a plurality of connectors and a plurality of kinds of integrated circuit cards adapted to be connected to the plurality of connectors. Fung et al. (U.S. Pat. No. 5,630,163, Computer Having A Single Bus Supporting Multiple Bus Architectures Operating With Different Bus Parameters, May 13, 1997) discusses a data processing system including a central processing unit and control circuitry on a single chip connected by a common bus to two or more bus devices having different sets of bus parameters. A second set of bus parameters functions as an I/O bus for I/O device transfers. Cohen et al. (U.S. Pat. No. 5,608,876, Add-In Board With Enable-Disable Expansion ROM For PCI Bus Computers, Mar. 4, 1997) discusses an adapter or add-in card for use in a peripheral component interconnect (PCI) computer, including a universal module which couples the card to the PCI bus. Young et al. (U.S. Pat. No. 5,548,730, Intelligent Bus Bridge For Input/Output Subsystems In A Computer System, Aug. 20, 1996) discusses an intelligent bus bridge including a local processor coupled for communication over a local component bus and a local memory controller that enables access to a local memory from the local component bus. LaBarbera (U.S. Pat. No. 5,488,705, Apparatus For Connecting Computer Devices, Jan. 30, 1996) discusses an integrated circuit capable of multiplexing and then serializing parallel bus and tag information received from one or more interfaces of one of the computer devices. Cutter (U.S. Pat. No. 5,488,695, Video Apparatus Board In Expansion Slot Independently Exercising As Bits Master Control Over System Bus In Order To Relief Control Of Host Computer, Jan. 30, 1996) discusses a video peripheral board having a video I/O port configured to connect a video device, a bus interface circuit, and a processor. From my study of the contemporary practice and art, I find that there is a need for an improved and effective connector system for components of a computer-based multimedia system.